Design and Implementation of 57-GHz Voltage-Controlled Oscillator, 24-GHz sub-harmonic I/Q demodulator

• Main Authors: Chuan-Wei Tsou, 鄒權煒
• Other Authors: Yo-Sheng Lin
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/43586407907588604181

碩士 === 國立暨南國際大學 === 電機工程學系 === 97 === The aim of this thesis is to design Voltage-Controlled Oscillator (VCO) and Sub-Harmonic Mixer (SHM). The research theme can be divided into two parts： In the first part, the 57-GHz VCO is designed for Phase Lock Loop (PLL) system application. Utilizing the tunable source-degeneration technique to decrease the MOS parasitic capacitor Cgs and increase the tuning range. The simulated results show that a tuning range is 1.52 GHz (from 51.39 GHz to 49.87 GHz) without using the tunable source-degeneration technique. After using this technique, a tuning range is 1.19 GHz (from 55.02 GHz to 53.83 GHz). There is few sacrifice for tuning range in this condition and we further enhance the tuning range of 2.94GHz (from 55.02 GHz to 57.96 GHz) with the ratio of enhancement is 247% (from 1.19 GHz to 4.13 GHz).The measured results show that the total tuning range is 3.88 GHz (from 53.36 GHz to 57.24 GHz) with the ratio of enhancement is 185.3% (from 1.36 GHz to3.88 GHz), which is close to the simulated result of 247%. The power consumption of the VCO core is 8 mW from the 0.8 V power supply. In addition, we design the second 57-GHz VCO. The differences between the first and the second VCO are described as below: first, the oscillation frequency increases with the increase of VT1, however, the built-in MOS varactor exhibits a poor quality factor while the capacitance decrease with the increase of VT1. As a result, we replace the built-in MOS varactor with the MOSFET whose source, drain and body are shortened. The simulation results show that using MOSFET with three regions shortened under the condition of close capacitance at 57 GHz can effectively increase the quality factor of 4 to 6. Second, we reduce the buffer stage to one common-source topology. The measured results show that the total tuning range is 1.6 GHz (from 55.4 GHz to 57 GHz), the ratio of enhancement is 33% (from 1.2 GHz to1.6 GHz), which is close to the simulated result of 38%. The power consumption of the VCO core is 6.24 mW from the 0.8 V power supply, the measured phase noise at 10 MHz offset from 55.8 GHz carrier is -105.72 dBc/Hz, which is suitable for high speed and low power MMW system application. In the second part, a 24-GHz sub-harmonic I/Q demodulator is implemented in standard TSMC 0.18 m CMOS technology for low-IF receiver application. The demodulator makes the use of stacked quadrature coupler and balance-unbalance convertor to achieve the needed phase difference. The measured results show that it has perfect isolation at 24 GHz (all greater than 40 dB), especially the LO-to-RF isolation is 61 dB. The measured conversion gain at 24 GHz is -2.75 dB and the 1-dB gain compression point is -3 dBm. The measured RF port return loss at 24 GHz is 10 dB and the LO port return loss at 12 GHz is 16 dB. The measured phase difference and amplitude imbalance are 86.47° and 0.6 dB. The total power consumption is 55.25 mW from the demodulator, which is suitable for low power radar systems. Besides, we design the Marchand balun testkey with bandwidth of 30 to 45 GHz in TSMC 0.13 um CMOS technology, whose measurement results are agree with the simulation results. In this bandwidth, the measured input and output return losses are both below -8 dB, the insertion loss with a range of 5.7 to 6.7 dB, the amplitude imbalance is below 1 dB, the phase difference is within 6.5°. The balun occupies an area of 51×108 mm2, which is very suitable for systems integration.