Design and Implementation of Transmission line Inductors, VCO and ILFD used in Frequency Synthesizer

• Main Authors: Tsung Yean Chen, 陳宗彥
• Other Authors: Yo-Sheng Lin
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/97515804774641189022

碩士 === 國立暨南國際大學 === 電機工程學系 === 97 === This thesis aim is the design and implementation of transmission line inductors, VCO and ILFD used in frequency synthesizer. The research subject can be divided into three parts： In first part, we design some transmission line inductors with metal ground shielding to reduce substrate loss when the inductors used in high frequency environment. The transmission line inductors were implemented by UMC 90nm CMOS technology and the measurement result shows the Q-factor of transmission line with ground shielding can be 71.69% higher than which without shield. The transmission line inductors can be used in high frequency environment. In the second part, we design two voltage control oscillators (VCOs) implemented by TSMC 0.18mm CMOS technology. One VCO achieves phase noise of -104.31 dBc/Hz at 1 MHz offset and operates the frequencies from 17.879GHz to 20.094GHz with a tuning voltage from 0 to 1.3V. The power consumption of this VCO core is only 10.582 mW. The figure-of merit (FOM) of the VCO is -180.09 dBc/Hz. Another one achieves phase noise of -98.64 dBc/Hz at 1 MHz offset and operates the frequencies from 24.058GHz to 26.042GHz with a tuning voltage from 0 to 1.5V. The power consumption of this VCO core is only 13.725 mW. The figure-of merit (FOM) of the VCO is -174.9 dBc/Hz. The last part, two Injection-Lock Frequency Dividers implemented by TSMC 0.13mm technology are presented. One is a low-power 64.76-GHz (V-band) injection-locked frequency-divider (ILFD) by using Shunt-Peaking technique and the other is a V-band direct Injection-Locked divide-by-three Frequency Divider. In the first divider to reduce power consumption and enhance locking range, a peaking inductor TL3 is connected to the internal node to resonate with the parasitic capacitor by transistors M1, M2 and M3 at input frequency. Therefore, the locking range will be enhanced by the internal power can be increased due to the increase of the impedance at the internal node. This ILFD architecture also features a very low input capacitance; thus, high operating frequency of 64.76 GHz can be achieved. This ILFD consumes 3.394 mW with locking range of 10.144 GHz (54.612~64.756 GHz) 17% and excellent sensitivity of -60dBm. The other divider is to divide-by-three ILFD, the injection part in this circuit is designed by two PMOS and two differential signals input in two PMOS gate point. On the other hand, the circuit core has one module of voltage control varactors for frequency tuning. In order to tune circuit free-running and makes it Wide-Bandwidth, the operating voltage of varactors can be changed. This ILFD consumes 4.56 mW with locking range of 3.132 GHz (38.231~41.363 GHz).