Scheduling Semiconductor In-line Steppers in New Product/Process Introduction Scenarios
博士 === 國立交通大學 === 工業工程與管理系所 === 97 === Abstract This dissertation examines job scheduling problems for in-line steppers operating in a new process/production introduction (NPI) scenario. An in-line stepper is a bottleneck machine in a semiconductor fab. Its interior is comprised of a series of chamb...
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ndltd-TW-097NCTU50310212015-10-13T14:53:17Z http://ndltd.ncl.edu.tw/handle/52331998935028036601 Scheduling Semiconductor In-line Steppers in New Product/Process Introduction Scenarios 半導體傳輸整合步進機在新產品/新製程導入情境下之排程 Chiou, Chie-Wun 邱志文 博士 國立交通大學 工業工程與管理系所 97 Abstract This dissertation examines job scheduling problems for in-line steppers operating in a new process/production introduction (NPI) scenario. An in-line stepper is a bottleneck machine in a semiconductor fab. Its interior is comprised of a series of chambers, while its exterior is a dock equipped with a limited number of ports. The transportation unit for each chamber is a piece of wafer while that for each port is a job that could contain up to 25 wafers. This transportation incompatibility may lead to an unexpected capacity loss for an in-line stepper—in particular in an NPI scenario that, by nature, includes a substantial number of small-sized jobs. Such a capacity loss can be alleviated by effective scheduling. This dissertation is composed of three parts. Firstly, we develop a genetic algorithm (GA), a kind of meta-heuristic algorithm, to solve the job scheduling problem for a single in-line stepper. Secondly, to enhance the solution quality, we develop some other meta-heuristic algorithms. Thirdly, we examine a job scheduling problem, in which jobs could be processed by multiple in-line steppers. This problem includes two decisions: job assignment and job sequencing. Through developing a new and concise representation scheme for modeling the two decisions, we solve the multiple-machine scheduling problem by various meta-heuristic algorithms. The preceding single-machine scheduling problem in fact is a special case of the multiple-machine scheduling problem. Extensive numerical experiments indicate that a GA-Tabu algorithm developed by us essentially outperforms the other meta-heuristic algorithms adopted from literature. Keywords: Semiconductor, In-line stepper, Scheduling, GA-Tabu, Flow shop, Port constraint, GA Wu, Muh-Cherng 巫木誠 2009 學位論文 ; thesis 101 zh-TW |
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博士 === 國立交通大學 === 工業工程與管理系所 === 97 === Abstract
This dissertation examines job scheduling problems for in-line steppers operating in a new process/production introduction (NPI) scenario. An in-line stepper is a bottleneck machine in a semiconductor fab. Its interior is comprised of a series of chambers, while its exterior is a dock equipped with a limited number of ports. The transportation unit for each chamber is a piece of wafer while that for each port is a job that could contain up to 25 wafers. This transportation incompatibility may lead to an unexpected capacity loss for an in-line stepper—in particular in an NPI scenario that, by nature, includes a substantial number of small-sized jobs. Such a capacity loss can be alleviated by effective scheduling.
This dissertation is composed of three parts. Firstly, we develop a genetic algorithm (GA), a kind of meta-heuristic algorithm, to solve the job scheduling problem for a single in-line stepper. Secondly, to enhance the solution quality, we develop some other meta-heuristic algorithms. Thirdly, we examine a job scheduling problem, in which jobs could be processed by multiple in-line steppers. This problem includes two decisions: job assignment and job sequencing. Through developing a new and concise representation scheme for modeling the two decisions, we solve the multiple-machine scheduling problem by various meta-heuristic algorithms. The preceding single-machine scheduling problem in fact is a special case of the multiple-machine scheduling problem. Extensive numerical experiments indicate that a GA-Tabu algorithm developed by us essentially outperforms the other meta-heuristic algorithms adopted from literature.
Keywords: Semiconductor, In-line stepper, Scheduling, GA-Tabu, Flow shop, Port constraint, GA
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Wu, Muh-Cherng |
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Wu, Muh-Cherng Chiou, Chie-Wun 邱志文 |
author |
Chiou, Chie-Wun 邱志文 |
spellingShingle |
Chiou, Chie-Wun 邱志文 Scheduling Semiconductor In-line Steppers in New Product/Process Introduction Scenarios |
author_sort |
Chiou, Chie-Wun |
title |
Scheduling Semiconductor In-line Steppers in New Product/Process Introduction Scenarios |
title_short |
Scheduling Semiconductor In-line Steppers in New Product/Process Introduction Scenarios |
title_full |
Scheduling Semiconductor In-line Steppers in New Product/Process Introduction Scenarios |
title_fullStr |
Scheduling Semiconductor In-line Steppers in New Product/Process Introduction Scenarios |
title_full_unstemmed |
Scheduling Semiconductor In-line Steppers in New Product/Process Introduction Scenarios |
title_sort |
scheduling semiconductor in-line steppers in new product/process introduction scenarios |
publishDate |
2009 |
url |
http://ndltd.ncl.edu.tw/handle/52331998935028036601 |
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