Built-in Self-test Circuit for Pipelined Analog to Digital Converter

• Main Authors: ChingLin Jang, 任慶霖
• Other Authors: ChauChin Su
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/92432185517825852498

碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 97 === New CMOS and digital signal processing techniques have a great variety of applications in recent years. Pipelined ADC is wildly utilized for its flexibility in speed, resolution, and power. In traditional converter’s static testing time consumption and hardware overhead of test equipment are still the prime concerns. In the thesis, a simple built-in self test is proposed for pipelined analog to digital converters. By taking the advantages of the structure in pipelined stage, we use the next stage comparators to scan the transfer curve of the previous stage. The stage gain error and offset error can be estimated. With certain confidence interval analysis reliable results can be achieved. A 8-bit 100MS/s pipelined ADC is realized to verify the algorithm. It is made of seven stages of 1.5-bit sub-converters and an 1-bit back end stage. The proposed pipelined ADC and BIST circuit are designed using TSMC 1P6M CMOS process with an active die area of . In normal operation the peak SNDR is with the input signal frequency of . The total power consumption of the proposed modulator is . In BIST mode, with intentional mismatch added into stage one and stage two, gain errors can be estimated correctly. Finally the Matlab is used to correct the error.