| Summary: | 碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 97 === This thesis is about memory (buffer) and we present a Sandwich Ping Pong Memory. The area in the Sandwich Ping Pong Memory is much less than in a Ping Pong Memory. Besides, it is more flexible on the operation frequency compared with a Ping Pong Memory. Data are written into the Sandwich Ping Pong Memory row by row and read from it column by column simultaneously. Based on March C- algorithm, we also developed the test algorithm for the Sandwich Ping Pong Memory and named it the modified March C- algorithm. It can detect the stuck-at fault, transition fault, address fault, and coupling fault. We also successfully taped out a 64-byte Ping Pong Memory in process 0.35 2p4m in National Chip Implementation Center (CIC). Finally, we do the verification and testing. As a result, the fault coverage is at 100% of each fault. The chip is 1310 x 1100 micro meters squared. In order to design the control unit, the area overhead is under five hundred gate counts at the range of Common Bar is under 512 unit memory cells.
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