On-Chip ESD Protection Designs for Radio-Frequency Integrated Circuits and High-Speed I/O Interface Circuits

• Main Author: 蕭淵文
• Other Authors: Ming-Dou Ker
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/11609082849025684177

博士 === 國立交通大學 === 電子工程系所 === 97 === With the continuous evolution of communication technology and integrated circuit (IC) process, wireless and wireline communication devices had become essential in daily life. By using the wireless communication devices to transmit data, users can access any information more conveniently. Advance wireline communication technology speedups the data transmission rate between the access points (AP) and the server. The continuous scaling of IC process technology further stimulates the demand for communication devices. All microelectronic products, including IC products, must meet the reliability specifications during mass production in order to be safely used and provide moderate life time. Electrostatic discharge (ESD), which has become one of the most important reliability issues in IC products, must be taken into consideration during the design phase of all IC products. Most of the failures and damages found in ICs were demonstrated to be related to ESD. To provide effective ESD protection for the IC, all pads which connect the IC and the external world need to be equipped with ESD protection circuits, including the input/output (I/O) pads, VDD pads, and VSS pads. However, the ESD protection devices at the I/O pads inevitably cause parasitic effects on the signal path. The radio-frequency (RF) front-end circuits in wireless communication devices need ESD protection design as well because they connect the RF transceiver to the external antenna or band-select filter. Since the RF front-end circuits operate in the frequency band ranging from several gigahertzes to tens of gigahertz, such a high operating frequency leads to strict limitations for the parasitic effects on the signal path. If the parasitic effects on the signal path are too large, RF circuit performance will be seriously degraded. Besides RF front-end circuits, the data rates of recent wireline communication standards also increase, so the parasitic effects on the signal paths of high-speed I/O interface circuits in wireline communication systems also need to be watched. The situation introduces the challenge in ESD protection design for RF circuits and high-speed I/O interface circuits, which is to achieve the highest ESD robustness with the smallest performance degradation. In other words, the parasitic effects of the ESD protection devices need to be minimized. Furthermore, the evolution of CMOS process increases the difficulty of ESD protection design. Advanced CMOS technologies not only increase the operating frequency of transistors but also reduce the noise of active devices and power consumption. With the continuous scaling of CMOS technology, the dimensions of CMOS devices are reduced, so more function blocks can be integrated into a single chip. This is the application of system on chip (SoC). However, ESD was not scaled down with the CMOS technology. MOS transistors fabricated in advanced CMOS processes have thinner gate oxide and thus lower gate-oxide breakdown voltage, so they are more vulnerable to ESD. Here comes the other design challenge, which is to reduce the voltage across the ESD protection devices under ESD stresses in advanced CMOS processes. The two aforementioned design challenges form the motivation of this dissertation. This dissertation begins at the design in the periphery of the IC, which is the bond pad, and enters the co-design of RF front-end and ESD protection circuits. Besides, this dissertation covers the whole-chip ESD protection design within a single chip and the investigation of board-level charged-device-model (CDM) ESD issue in IC products. The research topics including: (1) overview of previous works on ESD protection design for RF and high-speed I/O interface circuits, (2) ultra low-capacitance bond pad design, (3) ESD protection design for wideband distributed amplifier, (4) differential low-noise amplifier (LNA) with whole-chip ESD protection design, (5) ESD protection design for high-speed I/O interface circuits, and (6) investigation on board-level CDM ESD issue in IC products. In chapter 2, the published ESD protection designs for RF front-end circuits and high-speed interface circuits are overviewed. The designs are categorized with their individual advantages and disadvantages clearly analyzed. The RF performance degradation caused by ESD protection devices are illustrated with measured results. Besides, the characteristics of ESD protection devices under ESD stress conditions are quite important, because it determines the ESD robustness. The designs are categorized into three groups, which are the circuit solution, layout solution, and process solution. With the circuit technique, the impacts of parasitic effects caused by ESD protection devices on circuit performance can be significantly mitigated by impedance matching or impedance isolation. However, the increased chip area due to the extra components increases the fabrication cost. With the layout modification, the parasitic effects and dimensions of ESD protection devices can be moderately reduced. Since no extra component is used, the fabrication cost is lower than that with circuit technique. The third group is process modification. By modifying the doping concentration, the junction capacitance can be adjusted to reduce the parasitic effects of ESD protection devices. However, process modification is uncommon in general IC products. The design complexity, improved parasitic effect, ESD robustness, and area efficiency of all reported designs are compared in this chapter. Besides ESD protection devices, bond pads also cause impacts on circuit performance because of their parasitic capacitance. To mitigate the performance degradation, bond-pad capacitance needs to be minimized as well. A new low-capacitance bond pad structure in CMOS technology for RF applications is proposed in chapter 3. Three kinds of inductors stacked under the pad are used in the proposed bond pad structure. Experimental results in a 130-nm CMOS process have verified that the bond-pad capacitance is reduced due to the cancellation effect provided by the inductor embedded in the proposed bond pad structure. The bond-pad capacitance is reduced to almost 0 fF from 4.3 to 4.8 GHz. The proposed bond pad structure is fully compatible to general CMOS processes without any extra process modification. In chapter 4, two distributed ESD protection schemes are proposed and applied to protect distributed amplifiers against ESD stresses. Fabricated in a 0.25-μm CMOS process, the distributed amplifier with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 5.5 kV and machine-model (MM) ESD level of 325 V, while exhibits the flat-gain of 4.7 ± 1 dB from1 to 10 GHz. With the same total parasitic capacitance, the distributed amplifier with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level is over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9 ± 1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the wideband RF performances and high ESD robustness of the distributed amplifier can be successfully co-designed to meet the application specifications. Besides ESD protection design for wideband RF frond-end circuits, co-design of narrow band LNA and ESD protection circuit is proposed in chapter 5. A 5-GHz differential LNA is implemented in a 130-nm CMOS process, and several new ESD protection schemes are applied to this differential LNA. This is the first work which investigates the pin-to-pin ESD robustness of differential LNAs. All of the fabricated differential LNAs consume 10.3 mW from the 1.2-V power supply. The reference differential LNA without ESD protection has 16.2-dB power gain and 2.16-dB noise figure at 5 GHz. The conventional double-diode ESD protection scheme is realized for the differential LNA, which has 2.5-kV HBM and 200-V MM ESD robustness. The differential LNA with the double-diode ESD protection scheme has 17.9-dB power gain and 2.43-dB noise figure at 5 GHz. With the proposed double silicon-controlled rectifier (SCR) ESD protection scheme, the HBM and MM ESD levels are significantly improved to 6.5 kV and 500 V, respectively. Besides, the differential LNA with the double-SCR ESD protection has 17.9-dB power gain, and 2.54-dB noise figure at 5 GHz. Another proposed design uses an ESD bus between the differential input pads, which has 3-kV HBM and 100-V MM ESD robustness. The differential LNA with the proposed ESD bus has 18-dB power gain and 2.62-dB noise figure at 5 GHz. The ESD protection design using cross-coupled SCR devices between the differential input pads is also proposed. Besides providing ESD protection for a single input pad, pin-to-pin ESD protection is also achieved without adding any extra devices. This ESD protection scheme achieves 1.5-kV HBM and 150-V MM ESD levels, respectively. The power gain and noise figure of this differential LNA are 19.2 dB and 3.2 dB, respectively. By using other diodes beside the cross-coupled SCR devices, the turn-on efficiency of ESD protection devices can be enhanced. With the double diodes and the cross-coupled SCR devices, the ESD-protected differential LNA achieves 4-kV HBM and 300-V MM ESD robustness, and exhibits 19.1-dB power gain and 3-dB noise figure at 5 GHz. Chapter 6 presents the ESD protection design for high-speed I/O interface circuits. The ESD levels and parasitic capacitances of P+/N-well and N+/P-well ESD protection diodes with different dimensions are characterized in the beginning. Then the double-diode ESD protection scheme is applied to the dummy receiver NMOS and the dummy transmitter NMOS. Since the connection of the dummy receiver NMOS (dummy transmitter NMOS) is similar to that of the NMOS transistor in a receiver (transmitter) interface circuit, the ESD robustness of the dummy receiver NMOS (dummy transmitter NMOS) can be used to predict the ESD robustness of the high-speed interface circuit with this ESD protection scheme. This whole-chip ESD protection scheme is also applied to a 2.5-Gb/s high-speed I/O interface circuit, and the ESD robustness is larger than 3 kV in HBM with the parasitic capacitance of less than 250 fF. Moreover, a new ESD protection scheme is proposed in chapter 6. By replacing the N+/P-well diode between the input pad and VSS with the SCR, the ESD robustness can be further improved. In the ESD protection schemes in chapter 6, the ESD protection devices and part of the ESD detection circuit is placed under the I/O pad to reduce the chip area and the parasitic capacitance on the signal path. After finishing ESD protection design for a single chip, the chip needs to be installed in a module and module function test will be performed. At this time, board-level CDM ESD events may occur to damage the ICs. In chapter 7, the impacts caused by board-level CDM ESD events on IC products are investigated. The mechanism of board-level CDM ESD event is introduced first. Based on this mechanism, an experiment has been performed to investigate the board-level CDM ESD current waveforms under different sizes of printed circuit boards (PCBs), different charged voltages, and different series resistances in the discharging path. Experimental results have shown that the discharging current strongly depends on the PCB size, charged voltage, and series resistance. Moreover, chip-level and board-level CDM ESD levels of several test devices and test circuits fabricated in CMOS processes have been characterized and compared. Test results have shown that the board-level CDM ESD level of the test circuit is lower than the chip-level CDM ESD level, which demonstrates that the board-level CDM ESD event is more critical than the chip-level CDM ESD event. In addition, failure analysis reveals that the failure on the test circuit under the board-level CDM ESD test is much severer than that under the chip-level CDM ESD test. Chapter concludes the achievement in this dissertation, and suggests several future works in this field. Since the standard for the board-level CDM ESD test is not established so far, the proposal of the “Test standard for board-level charged-device-model electrostatic discharge robustness of integrated circuits” (in Chinese) is presented in the appendix. In the proposal, the test methodology and test conditions are clearly defined. In this dissertation, several novel designs have been proposed in the aforementioned research topics. Measured results of fabricated test chips have demonstrated the performance improvement. The achievements of this dissertation have been published in several international journal and conference papers. Several innovative designs have been applied for patents.