| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 97 === The thesis presents two solutions of the monolithically-integrated high-speed optical receivers in standard 180-nm CMOS technology. The optical receivers are capable of delivering 800 mVpp to 50 ohms output load after optical to electrical conversion.
For the first one, it integrates a spatially modulated light (SML) detector, a transimpedance amplifier (TIA), and a post limiting amplifier on a single chip. A 3.125 Gbps high speed operation is achieved by utilizing SML detector and adaptive analog equalizer (EQ). The total power dissipation is 175 mW, and the chip size is 0.7 mm2.
For the other, it also includes a photodetector, a TIA, and a post limiting amplifier on a single chip. A novel PIN detector is proposed and adopted in this design without technology modification. It can operate up to 2.5 Gbps without an equalizer. The total power dissipation is 138 mW, and the chip size is 0.53 mm2
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