On Distinguishing Process Corner for Yield Improvement in Memory Compiler Generated SRAM

碩士 === 國立交通大學 === 電子工程系所 === 97 === As the technology scales down to nanometer, the yield degradation caused by inter-die variations is getting worse. Using adaptive body bias is an effective method to eliminate the yield degradation, however we need to know a die having high threshold voltage or lo...

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Main Authors: Chia-Chi Hsiao, 蕭家棋
Other Authors: Hung-Ming Chen
Format: Others
Language:en_US
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/13124971355873543191
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spelling ndltd-TW-097NCTU54280532015-10-13T13:11:49Z http://ndltd.ncl.edu.tw/handle/13124971355873543191 On Distinguishing Process Corner for Yield Improvement in Memory Compiler Generated SRAM 區別製程邊界來提高記憶體編譯器產生出來的靜態隨機記憶體良率 Chia-Chi Hsiao 蕭家棋 碩士 國立交通大學 電子工程系所 97 As the technology scales down to nanometer, the yield degradation caused by inter-die variations is getting worse. Using adaptive body bias is an effective method to eliminate the yield degradation, however we need to know a die having high threshold voltage or low threshold voltage (also called process corner) in order to use this technique. Unfortunately, it is hard to detect the process corner when PMOS and NMOS variations are uncorrelated. In this thesis, we propose some improved circuits of delay monitor and leakage monitor for both PMOS and NMOS having inter-die variations, and are uncorrelated. The experimental results show that our circuits can clearly distinguish each process corner of PMOS and NMOS, thus improve the yield obviously by adopting correct body bias. Hung-Ming Chen 陳宏明 2008 學位論文 ; thesis 38 en_US
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description 碩士 === 國立交通大學 === 電子工程系所 === 97 === As the technology scales down to nanometer, the yield degradation caused by inter-die variations is getting worse. Using adaptive body bias is an effective method to eliminate the yield degradation, however we need to know a die having high threshold voltage or low threshold voltage (also called process corner) in order to use this technique. Unfortunately, it is hard to detect the process corner when PMOS and NMOS variations are uncorrelated. In this thesis, we propose some improved circuits of delay monitor and leakage monitor for both PMOS and NMOS having inter-die variations, and are uncorrelated. The experimental results show that our circuits can clearly distinguish each process corner of PMOS and NMOS, thus improve the yield obviously by adopting correct body bias.
author2 Hung-Ming Chen
author_facet Hung-Ming Chen
Chia-Chi Hsiao
蕭家棋
author Chia-Chi Hsiao
蕭家棋
spellingShingle Chia-Chi Hsiao
蕭家棋
On Distinguishing Process Corner for Yield Improvement in Memory Compiler Generated SRAM
author_sort Chia-Chi Hsiao
title On Distinguishing Process Corner for Yield Improvement in Memory Compiler Generated SRAM
title_short On Distinguishing Process Corner for Yield Improvement in Memory Compiler Generated SRAM
title_full On Distinguishing Process Corner for Yield Improvement in Memory Compiler Generated SRAM
title_fullStr On Distinguishing Process Corner for Yield Improvement in Memory Compiler Generated SRAM
title_full_unstemmed On Distinguishing Process Corner for Yield Improvement in Memory Compiler Generated SRAM
title_sort on distinguishing process corner for yield improvement in memory compiler generated sram
publishDate 2008
url http://ndltd.ncl.edu.tw/handle/13124971355873543191
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