| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 97 === Recently, many high-speed and low cost serial link transmission technologies are
developed and are widely used in modern electronic products. The clock and data
recovery module is the most important component in the receiver end of high speed
serial link systems. Modern trend of CDR circuit design includes: First, as the
increase of transmission bandwidth and the decrease of fabrication cost, multi-channel
transmission system has become the mainstream. Second, digitally implemented
CDRs are often more favorable than analog ones for the broad applications and
robustness against PVT (process, voltage, temperature) variations. Finally, in order to
reduce EMI (electro-magnetic interference) problem, spread spectrum clock
technology is used in data transmission. Therefore, it is necessary for CDR to recover
correct data from spread spectrum clock transmission.
In the high speed CDR, binary phase detection is the mainstream. However the
non-linear characteristic of binary phase detection introduces unwanted effects like
PD gain varies with jitter amplitude, and oscillatory steady state of phase tracking.
Therefore we propose a Multiple-Alternating Edge Sampling (M-AES) scheme and
Gain Compensation to linearize the PD gain and achieve a stable phase detection.
Spread spectrum technique slightly modulates the frequency of clock signal and
spreads it over a wider bandwidth. This would lead to a reduction of the peak level of
the clock energy. A spread spectrum technique using PLL with a sigma delta
modulator and phase rotation algorithm is proposed. Our spread spectrum clock
generator (SSCG) for Serial ATA III Specification is down spread 5000ppm with a
triangular modulation profile and the modulation frequency is 30 KHz. One objective
of this thesis is to analyze the effect of different order of ΣΔ modulation. Our
theoretical results have shown that, once the phase resolution of the interpolator is
high enough, the difference of the jitter from different order of modulators is so
insignificant that can be neglected.
The test chip is fabricated in UMC 90nm CMOS regular-Vt process. The
post-layout simulated data rate from 5.5Gbps to 6.5Gbps, the peak-to-peak jitter is
17.52ps. The spread clocking has a peak-to-peak cycle-to-cycle jitter of 1.13ps and
consumes 7.57mW at 1.4GHz. The EMI reduction in this circuit is about 20.6dB. The
analog circuit power consumption is 55mW under 1.0V supply voltage.
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