| Summary: | 博士 === 國立交通大學 === 電子工程系所 === 97 === Following the progress of advanced technology, the channel length of MOS
transistor is smaller and the parasitic is also reduced. These characteristics
make the transistor be able to be operated in higher frequency and lower power
dissipation. However, the output impedance of MOS transistor
reduces with the channel length. In addition to the output impedance,
the thickness of gate oxide also becomes thinner than a long channel device.
For device reliability issue, supply voltage scales down with channel
length. The reduced output impedance and supply voltage make analog circuits
can not be designed with high gain and large dynamic range. These features make
the design of high performance analog circuits more difficult.\\
Voltage-mode switched-capacitor (SC) pipelined ADC is widely used. This circuit
is operated with high gain operation amp (opamp) and configures in negative feedback.
The negative feedback circuit can achieve high linearity and high accuracy at the
same time. However, with capacitor mismatch and finite opamp's dc gain, the output
of a pipelined ADC may contain servere nonlinearity. The capacitor matching with
present CMOS technology can be used to design a pipelined ADC with 10-12 bit resolution.
But it's hard to design a high gain opamp with high unit-gain frequency
in deep-submicron technology. The main purpose of this thesis is to design a high
performance pipelined ADC in deep-submicron technology.\\
This thesis presents a background calibration scheme for pipelined
analog-to-digital converters (ADCs) that is robust.
For a SC pipeline stage, by
splitting its input sampling capacitor, a random sequence can be
injected into the ADC's signal path, and then calibration data can
be extracted from the ADC's digital output without interrupting its
normal conversion operation. Using an input-dependent scheme to
generate the calibration random sequence, no additional signal range
is required to accommodate the extra calibration signal.\\
A 32-mW 12-bit 80-MS/s pipelined ADC was fabricated using a 65~nm
CMOS technology. The ADC demonstrates a new digital background
technique, which corrects pipeline stage nonlinearity as well as
gain and sub-DAC errors. The proposed technique is robust and
immune to device mismatches, and does not need extra signal range.
Since the accuracy and linearity requirements are mitigated, analog
circuits with less complexity and power can be used. The ADC achieves
67~dB SNDR and 81~dB SFDR at 80~MS/s sampling rate with a 2~MHz
sinewave input. \\
In addition, a split-channel ADC architecture is proposed to reduce the
calibration time. The split-channel ADC consists of two A/D
channels that receive the same analog input but employ different
random sequences for calibration. The calibration time can be
greatly reduced by comparing the digital outputs from both channels
and then removing the embedded perturbations before extracting the
calibration data. The proposed calibration techniques are analyzed
by using both theoretical formulation and system-level simulation.
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