| Summary: | 博士 === 國立交通大學 === 機械工程系所 === 97 === In this work, gate stack formation for high-k materials, spacer process improvement and stress enhancement process before SiGe growth are proposed. The first two processes can improve the performance of pMOSFET and nMOSPET, and the third process can improve the pMOSFET performance.
In gate stack formation, one feasible process flow integrating high-k and metal gate to decrease Jg (gate leakage) and EOT (electrical oxide thickness) without further impacting mobility is proposed, where dual work function metal gate can be formed by the proposed flow.
For spacer process improvement, instead of using conventional silane-based nitride, disilane-based nitride is proposed to use on spacer here, since the disilane precursor is non-sensitive to temperature. The experimental results show the improvements on thickness uniformity by 68% and uniformity on Idsat variation by 9%. The throughput enhancement and thermal budget reduction are also achieved.
In SiGe growth, an improved pre-treatment process is proposed by performing cyclical O3/DHF clean, low temperature HCl bake and Si seed growth prior to SiGe growth. Then the in-situ boron-doping SiGe is deposited with dislocation free. It is shown that hole mobility is enhanced around 2.4 times. Furthermore, combined effects from enhanced mobility provided by compressive local stress and in-situ boron doping to decrease contact resistance contribute the Ion gain enhancement around 32% for pMOSFET.
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