Process development on high-k gate stack, spacer formation and SiGe growth for CMOS performance enhancement
博士 === 國立交通大學 === 機械工程系所 === 97 === In this work, gate stack formation for high-k materials, spacer process improvement and stress enhancement process before SiGe growth are proposed. The first two processes can improve the performance of pMOSFET and nMOSPET, and the third process can improve the p...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/58480567650914265988 |