A Radix-4 LDPC Decoder for 802.11n

• Main Authors: Chen Yu-Wen, 陳宇文
• Other Authors: Tsai Shang-Ho
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/91262333307134435573

碩士 === 國立交通大學 === 電機與控制工程系所 === 97 === In this thesis, a new decoding algorithm called Radix-4 LDPC decoder is used to increase the throughput and achieve better BER performance. Moreover, a three-size (1944,972), (1296,648), and (648,324) LDPC decoder applied to IEEE 802.11n standard is implemented. The partially parallel scheme is used to decrease chip area as well as routing resource. The LDPC decoder was implemented with TSMC CMOS 18um process. The proposed decoder can achieve 292∼50Mbps decoding throughput rate under clock frequency of 62.5MHz. The core size is 17.9 mm2 and average power consumption with a 1.62V voltage supply is 145mW.