Chip Design of Low-Power Voltage-Controlled Oscillators with Tuning Range
碩士 === 國立彰化師範大學 === 積體電路設計研究所 === 97 === In this thesis, the designed two voltage-controlled oscillators are operating at various oscillation frequencies. All the circuit designs are based on TSMC 0.18μm CMOS standard technology model. First, we propose a VCO with low power and low phase noise. Th...
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| Format: | Others |
| Language: | zh-TW |
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2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/96330206220718135030 |
| Summary: | 碩士 === 國立彰化師範大學 === 積體電路設計研究所 === 97 === In this thesis, the designed two voltage-controlled oscillators are operating at various oscillation frequencies. All the circuit designs are based on TSMC 0.18μm CMOS standard technology model.
First, we propose a VCO with low power and low phase noise. The designed circuit is a 10GHz VCO based on current-reuse architecture. A noise filter is introduced in the VCO to enhance the phase noise performance of VCO.The simulated phase noise is -114.8dBc/Hz at 1MHz offset away from the oscillation frequency of 10GHz. The VCO-core power consumption is 0.88mW. The frequency can be tuned between 9~10.2GHz.
Second, we propose a wide-band and low power CMOS VCO based on current-reuse architecture and Transconductance-Match technique for 8GHz application. The Transconductance-Match technique is introduced in the VCO to enhance the amplitude-balance of VCO. Simulation results show that the VCO can be tuned between 7.1 to 9.2GHz with 0.47mW power consumption.
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