| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 97 === The Discrete Cosine Transform (DCT) is widely used tool in many digital signal and image processing applications due to its energy concentration properties. Recently, people are required the more quality of image to satisfy them. Thus, the ability of high speed computation is needed to deal with enormous image data. Therefore, the design of DCT for processing efficiency is a very important issue. On the other hand, because of the rapid in semiconductor fabrication technology, a large number of transistors can be incorporated into a single chip. However, this will reduce the controllability and observability of the chip significantly. As a result, testing such a highly complex and dense circuit becomes very difficult and expensive. Therefore, I propose an efficient design for testability (DFT) technique based on the residue/quotient (RQ) codes for the 2D DCT processors in this thesis. Based on the RQ codes, the DCT is implemented by the residue processing elements and the quotient processing elements to speed up the computation. Besides, a large dynamic range binary system can be partitioned into two faster parallel operations with small dynamic range in the residue processing elements and the quotient processing elements. The decimal DCT can improve throughput to 76.4%. For circuit testing consideration, I design for testability of 2D-DCT based on RQ codes. The proposed testability DCT have very low overhead.
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