Study on Scaling Capability of Nanowire Transistors

• Main Authors: Chun Yu Chen, 陳俊佑
• Other Authors: Meng-Hsueh Chiang,Shiou-Ying Cheng
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/06479724790748063412

碩士 === 國立宜蘭大學 === 電子工程學系碩士班 === 97 === The thesis mainly focuses on the scaling capability of the nanowire transistors, and the impact of quantum effect is investigated via physical 3D numerical simulation. We analyze the channel scalability and discuss how to control the short channel effects of nanowire, FinFET and Tri-Gate transistors characteristics. Several emerging patterning processes have been proposed in recent years. Due to device size scaling, quantum mechanical effects become significant. The physical quantum mechanical model is one of key figures for 3D numerical device simulation. The quantum mechanical model is analytically studied and compared with classical model. The characteristics of electron distributions on different surface orientations subject to film thickness and manufacturability of the nanowire device are investigated via 3D numerical simulation. We comprehensively examine the three types of multiple-gate structures including nanowire, FinFET and Tri-Gate devices. In order to evaluate the device performance when considering speed for logic application, the thesis also focuses on CV/Ion for CMOS inverter with advanced multiple-gate devices.