Design and Implementation of A Low-Power, Small Memory Area, and Multi-Standard FFT Processor for MIMO OFDM Communication System

• Main Authors: Chen,Tang-Cheng, 陳堂政
• Other Authors: Chang,Tsin-Yuan
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/61262376459730355738

碩士 === 國立清華大學 === 電機工程學系 === 97 === Wireless communication plays a significant role in people’s life nowadays. FFT processor is the key module in the all OFDM communication systems. Due to the huge complex computations, the conventional FFT processor has larger area and higher power consumption. Thus, low power and small area are interesting issues. Our proposed FFT processor is composed of the MRMMDF module and the multibutterfly module. The multibutterfly module can operate the radix-2, radix-22, radix-23, or radix-24 butterfly according to different FFT sizes. The MRMMDF module can deal with simultaneously the four 128-point FFTs, and it has faster operation speed and higher throughput. The saturation check units and block floating-point units truncate timely the longer wordlength such that the wordlength of data are not increased continuously. The constant multiplier reduces helpfully the complexity, hardware area, and power consumption of general multiplier. The proposed FFT processor is implemented by using Faraday 90nm cell library in UMC 90nm 1P9M process. The core size is 1362x1362 um2. The power consumption is 16.2 mW at 40 MHz, and its power efficiency is very high. It can process correctly multiple data streams at 40 MHz, so it supports 4x4 MIMO 802.11n and 2x2 MIMO 802.16e standards. The SQNR is 50.45 dB when performing the 2048-point FFT. And it only needs 2.25N-word single-port memory and 1.75N-word dual-port memory, where N is 2048, for continuous flow design.