High-Speed DSP Circuit Design using Frequency Overscaling and Subword Detection Processing

• Main Authors: Cheng,Ying-Kuang, 鄭螢光
• Other Authors: Huang,Yuan-Hao
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/37796099239938960195

碩士 === 國立清華大學 === 電機工程學系 === 97 === The high speed circuit design is an imperative issue for advanced communication systems. Because of the requirement of high speed and high quality data transmission, high speed circuit design becomes an important research field. In the thesis, we utilize the frequency overscaling (FOS) technique to increase the operating frequency of the circuit. However, the FOS causes timing violation and degrades SNR performance greatly. In order to alleviate SNR degradation, we employ two techniques to combat the error noise generated by the timing violation. One is the system-level technique, and the other is the arithmetic-level technique. In the system level, the reduced-precision redundancy (RPR) is used to improve the clock speed with acceptable noise increase. It employs the reduced-precision replica of main DSP module as the estimator to detect and correct the error. In the arithmetic level, we propose a subword-detection processing (SDP) which can adjust datapth arithmetic timing by detecting the magnitude of the input signal, that is, the SDP technique can reduce the computation critical delay, and thereby result in the reduction of the probability of timing violation. Based on the RPR-based architecture and the SDP technique, we design an RPR-based SDP FFT processor to realize the high-speed DSP circuit using the FOS. The experimental results show that the SNR performance can be improved by 34.5 dB when the operating frequency is overscaled to 1.21 times of the maximal achievable frequency below which the timing violation does not exist.