| Summary: | 博士 === 國立清華大學 === 電機工程學系 === 97 === Embedded static random access memory (SRAM) in advanced nanometer complementary metal-oxide-semiconductor (CMOS) technology for microprocessor, application-specific integrated circuit (ASIC), and system-on-chip (SoC) has been encountering yield crisis due to increased die-to-die and within-die threshold voltage (Vt) variations, which may deteriorate DC electrical parameters such as static noise margin (SNM) and write margin. Moreover, prominent leakage currents incur more static power consumption and degrade signal integrity. For example, decreased on-current to off-current ratio owing to excessive bit-line leakage may result in sensing failure, i.e., incorrect read operation. Recently, numerous circuit design techniques have been proposed to expand operating margin of bit cells so as to diminish read and write failures. However, circuit design techniques to cope with sensing failure are still insufficient. Therefore, we developed some techniques to deal with sensing failure. X-calibration scheme aims at addressing the bit-line leakage problem. BIST-assisted timing-tracking (BATT) scheme provides robust timing control to alleviate sensing failure caused by latch-type sense amplifiers. Automatic-power-down (APD) sense amplifier avoids sensing failure and suppresses extravagant static power consumption for conventional current-mirror sense amplifiers. Furthermore, the on-chip self-VDD-tuning scheme not only automatically tunes the supply voltage of an SRAM macro to the minimum value but also tolerates temperature variation.
Measurement results from fabricated chips demonstrate that the SRAM macro adopting X-calibration scheme can cope with up to 320μA bit-line leakage (4.18 times larger than the baseline SRAM macro) and that BATT scheme can warrant correct functionality of the SRAM design under some injected variations. Additionally, simulation results of a 64Kb SRAM design using the APD sense amplifier in a 22-nm predictive technology model (PTM) show that power reduction of 28%-87% over the traditional current-mirror sense amplifier is achievable. Simulation results in a 0.18-μm CMOS process show that a 64Kb SRAM macro employing the self-VDD-tuning scheme with speed margining can tolerate temperature variation up to 125℃. Measurement results from a test chip in a 0.18-μm CMOS process confirm that an 8Kb SRAM macro can achieve 40% power reduction at 150MHz by means of the resilient self-VDD-tuning scheme. Consequently, incorporating our techniques with the previously reported read/write assist techniques can provide a robust SRAM design against process, voltage, and temperature (PVT) variations, thus improving SRAM yield.
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