A 1.2V 5.1GHz BIST Triple-State Very Fast Locking with Fractional-Spur-Eliminated PLL
碩士 === 國立清華大學 === 電機工程學系 === 97 ===
Main Authors: | Chiu, Shih-Wen, 邱仕文 |
---|---|
Other Authors: | Chang, Tsin-Yuan |
Format: | Others |
Language: | en_US |
Published: |
2009
|
Online Access: | http://ndltd.ncl.edu.tw/handle/68058924044739688950 |
Similar Items
-
5.5GHz Fast Lock All Digital PLL Design
by: Chia-Chun - Lin, et al.
Published: (2016) -
Design of Fast-Locking PLL Combined with DLL for 1.8 GHz Wireless Communication System
by: Ting-LinWu, et al.
Published: (2015) -
A Fast Lock Technique for the 5Ghz Wide band PLL Frequency Synthesizer Design
by: Guan-Wei Ke, et al.
Published: (2013) -
Fast locking PLL with all-digital locked-aid circuit
by: Fu-Jen Hsieh, et al.
Published: (2010) -
Spur Reduction of 1.5GHz Frequency Synthesizer by using Delay-locked Loop techniques
by: Chia-hui Lin, et al.
Published: (2016)