| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 97 === In this thesis, a high throughput fixed complexity soft-output sphere decoder supporting QPSK, 16-QAM, and 64-QAM modulation in the 4x4 MIMO system is proposed.
For achieving soft-output, the proposed tree search algorithm is presented. Some simulation results help to modify the tree search algorithm of the original fixed-complexity sphere decoder (FSD) for soft-output detection. Compared with the optimal soft-output sphere decoder, the proposed soft-output FSD (SFSD) has a little frame error rate (FER) degradation (0.5dB), but the benefit is that SFSD has fixed complexity and can suit to a parallel or full pipeline hardware design.
Moreover, a high throughput hardware architecture is proposed to implement the SFSD algorithm. A simplified enumeration method is proposed to reduce the hardware complexity. The parallel architecture is proposed to achieve high throughput. For the high clock frequency, many pipelines are inserted into the proposed architecture.
In addition, the proposed SFSD is implemented by the 0.18um CMOS cell-library of HP laboratory. The area of proposed hardware implementation is about 100k equivalent gates corresponding to the two-input drive-one NAND gate. The maximum throughput can reach to 120Mbps with 16-QAM modulation. Finally, the FPGA emulation is made to verify the proposed design is able to work. Then a high performance high throughput soft-output MIMO detector has completely accomplished in the thesis.
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