Effects of Metal Gate and High-k Blocking Layer on Charge-Trapping Flash Memory Devices
碩士 === 國立清華大學 === 工程與系統科學系 === 97 ===
Main Authors: | Lin, Hsiao-Len, 林孝倫 |
---|---|
Other Authors: | Chang-Liao, Kuei-Shu |
Format: | Others |
Language: | zh-TW |
Published: |
2009
|
Online Access: | http://ndltd.ncl.edu.tw/handle/85788773007853849370 |
Similar Items
-
Process Study of Trapping and Blocking Layers on Gate-All-Around Junctionless Charge Trapping Flash Memory Devices
by: Cheng, Chia-Hsin, et al.
Published: (2016) -
Effects of Stacked High-k Blocking Layer on Charge-Trapping Flash Memory Devices
by: Shiu, Feng-Wen, et al.
Published: (2010) -
Operation of enhancement on charge trapping flash memory devices with integration metal gate and blocking layer and Si-Ge channel
by: Yuan-Bin Chung, et al.
Published: (2008) -
Effects of Stacked High-K Charge trapping layers on Charge Trapping-type Flash Memory Device
by: Tsai, Tzu-Ting, et al.
Published: (2009) -
The High-k Charge Trapping Layer in Flash Memory Application
by: Ching Hua Huang, et al.
Published: (2011)