| Summary: | 博士 === 國立臺灣大學 === 電子工程學研究所 === 97 === With the progress in multimedia devices, the trend of video coding not only focuses on compression efficiency but also take video functionality into consideration. In this dissertation, video encoder is classified into two categories, high definition video coder and scalable video coder. Then, the combined high definition scalable video encoder chip is discussed. In each part, the discussion includes algorithm modification, data reuse strategy, and architecture design for memory-related issues, hardware cost and power consumption which are the main evaluated topics for video encoder system.
In the first part dissertation, H.264/AVC high profile is taken as case study for high definition and high quality video. For temporal prediction, we consider Bframe scheme and propose frame-parallel encoding scheme to process B-frames in parallel so that the required system memory bandwidth for temporal prediction can be largely saved. For spatial prediction, the open-loop algorithm is developed and the reconfigurable architecture is designed to achieve high profile and HDTV1080p specification.
In the second part of dissertation, the three video scalability of scalable video coding and their corresponding coding algorithms and architectures are discussed individually. For temporal scalability, first, we propose the fast decision strategy to dynamically find the best GOP size for multi-level coding scheme with almost no computation complexity overhead. Then, we analyze the coding structure and coding performance of open-loop multi-level coding schemes and conventional closed coding schemes, and propose an efficient combined hardware architecture for both MCTF and MCP with computation scalability property. For spatial scalability, to solve the doubled computation complexity from inter-layer residual prediction, we propose an IME-simplified scheme and explore the data reuse scheme in transformed domain to achieve the 40% FME hardware cost reduction. For quality scalability, to reduce the frame-level scan order and enormous system memory bandwidth from FGS, we propose three design techniques and layer-wised architecture to save 88 to 92% system memory bandwidth reduction with low hardware cost.
In the last part of dissertation, we combine the high definition specification from H.264/AVC high profile and the three scalabilities from H.264/AVC scalable extension to provide a general scalable video source for ambient environment which is composed of various display devices of totally different specifications. This chip is implemented on a 16:76mm2 die with UMC 90nm process and dissipates 306/411mW at 120/166MHz for high profile and SVC encoding. Compared to previous baseline encoders, our proposed encoder can save 20% to 30% bit rate in single-layer high profile coding and support temporal, spatial, and quality scalability in SVC profile.
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