0.5V MTCMOS Technique TSPC Dynamic Logic Circuit using for a Multiplier Design
碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === This thesis reports BP-DTMOS/MTCMOS technology used in the full adder and the multiplier for optimization of power consumption and speed performance. First， evolution trends of CMOS technique and the low voltage operation requirement of VLSI circuit are describe...
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2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/24800048978462663543 |
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ndltd-TW-097NTU054280412016-05-04T04:16:42Z http://ndltd.ncl.edu.tw/handle/24800048978462663543 0.5V MTCMOS Technique TSPC Dynamic Logic Circuit using for a Multiplier Design 使用0.5V多重臨界電壓技術單相位時序(TSPC)動態邏輯電路於乘法器設計 Chun-Yuan Chien 錢群元 碩士 國立臺灣大學 電子工程學研究所 97 This thesis reports BP-DTMOS/MTCMOS technology used in the full adder and the multiplier for optimization of power consumption and speed performance. First， evolution trends of CMOS technique and the low voltage operation requirement of VLSI circuit are described. Then BP-DTMOS technology is introduced. Chapter 2 describes the principle of low voltage dynamic logic circuit with and without latch using BP-DTMOS/MTCMOS technology. In addition， a full adder circuit using BP-DTMOS/MTCMOS technology is described. In Chapter 3， a dynamic logic circuit and DTMOS/MTCMOS technology pipelined multiplier using the 0.5V true single-phase clock (TSPC) is described. Chapter 4 is the conclusion and future work of this research. 郭正邦 2009 學位論文 ; thesis 49 zh-TW |
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碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === This thesis reports BP-DTMOS/MTCMOS technology used in the full adder and the multiplier for optimization of power consumption and speed performance. First， evolution trends of CMOS technique and the low voltage operation requirement of VLSI circuit are described. Then BP-DTMOS technology is introduced. Chapter 2 describes the principle of low voltage dynamic logic circuit with and without latch using BP-DTMOS/MTCMOS technology. In addition， a full adder circuit using BP-DTMOS/MTCMOS technology is described. In Chapter 3， a dynamic logic circuit and DTMOS/MTCMOS technology pipelined multiplier using the 0.5V true single-phase clock (TSPC) is described. Chapter 4 is the conclusion and future work
of this research.
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| author2 |
郭正邦 |
| author_facet |
郭正邦 Chun-Yuan Chien 錢群元 |
| author |
Chun-Yuan Chien 錢群元 |
| spellingShingle |
Chun-Yuan Chien 錢群元 0.5V MTCMOS Technique TSPC Dynamic Logic Circuit using for a Multiplier Design |
| author_sort |
Chun-Yuan Chien |
| title |
0.5V MTCMOS Technique TSPC Dynamic Logic Circuit using for a Multiplier Design |
| title_short |
0.5V MTCMOS Technique TSPC Dynamic Logic Circuit using for a Multiplier Design |
| title_full |
0.5V MTCMOS Technique TSPC Dynamic Logic Circuit using for a Multiplier Design |
| title_fullStr |
0.5V MTCMOS Technique TSPC Dynamic Logic Circuit using for a Multiplier Design |
| title_full_unstemmed |
0.5V MTCMOS Technique TSPC Dynamic Logic Circuit using for a Multiplier Design |
| title_sort |
0.5v mtcmos technique tspc dynamic logic circuit using for a multiplier design |
| publishDate |
2009 |
| url |
http://ndltd.ncl.edu.tw/handle/24800048978462663543 |
| work_keys_str_mv |
AT chunyuanchien 05vmtcmostechniquetspcdynamiclogiccircuitusingforamultiplierdesign AT qiánqúnyuán 05vmtcmostechniquetspcdynamiclogiccircuitusingforamultiplierdesign AT chunyuanchien shǐyòng05vduōzhònglínjièdiànyājìshùdānxiāngwèishíxùtspcdòngtàiluójídiànlùyúchéngfǎqìshèjì AT qiánqúnyuán shǐyòng05vduōzhònglínjièdiànyājìshùdānxiāngwèishíxùtspcdòngtàiluójídiànlùyúchéngfǎqìshèjì |
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