Algorithms and VLSI Designs of Area-Efficient Reconfigurable Convolutional Turbo Decoder

• Main Authors: Cheng-Hung Lin, 林承鴻
• Other Authors: 吳安宇
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/80660130497430100531

博士 === 國立臺灣大學 === 電子工程學研究所 === 97 === With the rapid growth of multimedia services, convolutional turbo codes (CTCs) have been widely adopted as one of forward error correcting (FEC) schemes for wireless communications to have a reliable transmission over noisy channels. Most of advanced wireless standards have adopted distinct CTC schemes, such as single-binary (SB) CTC or double-binary (DB) CTC, with various block sizes and throughput rates. Thus, a reconfigurable and area-efficient dedicated hardware design for multistandard CTC decoding is necessary. To perform the alternative parallel-window (PW) and hybrid-window (HW) maximum a posteriori algorithm (MAP) decoding, three area-efficient combinations of PW and HW MAP decoding are proposed in this dissertation. To verify the proposed approach, a 1.28 mm2 dual-mode (SB/DB) 2PW-1HW MAP processor is implemented in 0.13 μm CMOS process. The prototyping chip achieves a maximum throughput rate of 500 Mbps at 125 MHz with an area efficiency of 3.13 bits/mm2. For the multistandard systems, the expected throughput rates of the WiMAX and LTE CTC schemes is achieved by using five dual-mode 2PW-1HW MAP processors. The iterative decoding of CTC has a large memory power consumption. To reduce the power consumption of the state metrics cache (SMC), low-cost and low-power memory-reduced traceback MAP decoding is proposed. For double-binary (DB) MAP decoding, radix-2x2 and radix-4 traceback structures are introduced to provide a tradeoff between power consumption and operating frequency. These two traceback structures achieve an around 7% power reduction of the DB MAP decoders. A high-throughput 12-mode WiMAX CTC decoder applying the proposed radix-2x2 traceback structure is implemented by using a 0.13 μm CMOS process in a core area of 7.16 mm2. Based on post-layout simulation results, the proposed decoder achieves a maximum throughput rate of 115.4 Mbps at 100 MHz with an area efficiency of 0.18 bits/mm2 and an energy efficiency of 0.43 nJ/bit per iteration. Finally, dual-mode (SB/DB) radix-4 MAP decoding is proposed. The computational modules and storages of the dual-mode (SB/DB) MAP decoding are designed to achieve a high area utilization. The proposed dual-mode MAP decoding can achieve around 45% silicon area reductions compared with the hardware non-shared radix-4 SB MAP and radix-4 DB MAP decoding. To verify the proposed approaches, a 3.38 mm2 35-mode WiMAX/LTE CTC decoder is implemented in 90 nm CMOS process. The prototyping chip achieves a maximum throughput rate of 241.2 Mbps at 164 MHz with an area efficiency of 0.43 bits/mm2. To the best of our knowledge, the prototyping decoder chip is the first CTC decoder to meet the throughput rate requirements of WiMAX and LTE CTC schemes. In summary, the proposed three designs of the area-efficient CTC decoding are applied to the CTC schemes of advanced communication systems. To verify the proposed designs for the prevalent communication standards, three prototyping implementations of CTC decoding are presented in this dissertation.