Design of a Network-on-Chip Architecture with Dynamically Reconfigurable Channels
碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication while supporting prioritized traffics in the network. The BiNoC allows each communication channel to be dynamically self-configured to t...
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/41884582431000916895 |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication while supporting prioritized traffics in the network. The BiNoC allows each communication channel to be dynamically self-configured to transmit flits in either direction in order to better utilize on-chip hardware resources. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate at each on-chip router. In this Thesis, a novel on-chip router architecture supporting the self-configuring bidirectional channel mechanism is presented. It is shown that the associated hardware overhead is negligible. Cycle-accurate simulation runs on this BiNoC network under synthetic and real-world traffic patterns demonstrate consistent and significant performance advantage over a conventional mesh grid NoC architecture equipped with hard-wired unidirectional channels.
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