The Design of Static Random Access Memory (SRAM) Compiler
碩士 === 南台科技大學 === 電子工程系 === 97 === Nowadays, due to the technology development grows rapidly, the requirement for the memory and its capacity in portable devices such as mobile phone or PDA is increasing progressively. However, the method of designing SRAM (Static Random Access Memory) by full custo...
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ndltd-TW-097STUT04280292016-11-22T04:13:06Z http://ndltd.ncl.edu.tw/handle/84670824746678763709 The Design of Static Random Access Memory (SRAM) Compiler 靜態隨機存取記憶體編譯器設計 Lung-Feng Tsai 蔡榮峯 碩士 南台科技大學 電子工程系 97 Nowadays, due to the technology development grows rapidly, the requirement for the memory and its capacity in portable devices such as mobile phone or PDA is increasing progressively. However, the method of designing SRAM (Static Random Access Memory) by full custom methodology will increase the working hours and the cost. Due to these problem we proposed a SRAM compiler that can generate layout automatically. The compiler will generate the SRAM layout automatically according to user’s inputs selected by users. We have established the leaf cells such as row decoders, column decoders, core cells, clock buffers and word line buffers for the cell library. We have designed various dimension of leaf cells in each part, and then analysis their timing delay. The timing analysis provides the compiler to generate the optimal SRAM layout. Tzyy-Kuen Tien 田子坤 2009 學位論文 ; thesis 53 zh-TW |
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碩士 === 南台科技大學 === 電子工程系 === 97 === Nowadays, due to the technology development grows rapidly, the requirement for the memory and its capacity in portable devices such as mobile phone or PDA is increasing progressively. However, the method of designing SRAM (Static Random Access Memory) by full custom methodology will increase the working hours and the cost. Due to these problem we proposed a SRAM compiler that can generate layout automatically.
The compiler will generate the SRAM layout automatically according to user’s inputs selected by users. We have established the leaf cells such as row decoders, column decoders, core cells, clock buffers and word line buffers for the cell library. We have designed various dimension of leaf cells in each part, and then analysis their timing delay. The timing analysis provides the compiler to generate the optimal SRAM layout.
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Tzyy-Kuen Tien |
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Tzyy-Kuen Tien Lung-Feng Tsai 蔡榮峯 |
author |
Lung-Feng Tsai 蔡榮峯 |
spellingShingle |
Lung-Feng Tsai 蔡榮峯 The Design of Static Random Access Memory (SRAM) Compiler |
author_sort |
Lung-Feng Tsai |
title |
The Design of Static Random Access Memory (SRAM) Compiler |
title_short |
The Design of Static Random Access Memory (SRAM) Compiler |
title_full |
The Design of Static Random Access Memory (SRAM) Compiler |
title_fullStr |
The Design of Static Random Access Memory (SRAM) Compiler |
title_full_unstemmed |
The Design of Static Random Access Memory (SRAM) Compiler |
title_sort |
design of static random access memory (sram) compiler |
publishDate |
2009 |
url |
http://ndltd.ncl.edu.tw/handle/84670824746678763709 |
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