Pipelined A/D Converter Design Automation

• Main Authors: Wen-Hsiang Wu, 吳文祥
• Other Authors: 邱弘緯
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/6j64e5

碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 97 === Pipelined A/D converter Design Automation from system to circuit is presented inthis paper. The pipelined A/D converter design flow can be separated into the system and circuit level design. It often adopts Matlab Simulink for the system level design ,makes simulation modules to realize a current system and simulates non-idea effects.Besides, we used simulated annealing algorithm to find the system parameters out and to achieve design optimization.We utilizes circuit simulator like Cadence Spectre for the circuit level design,apples software Neocircuit to design the circuit system and to optimize power dissipation. We have successfully implemented this automation flow for the 10-bits 50MSPS pipelined A/D converter with the simulated annealing algorithm. The final SNDR of the automatically designed shows up to 61dB,ENOB=9.8bits@5MHz,|DNL|<0.466 (LSB),INL less than 1.39(LSB).By using Neocircuit to optimize power dissipation, power dissipation=28mW by TSMC 0.18um CMOS technology.