Design of VLSI Architecture for Reed Solomon Codec

• Main Authors: Shih-Chieh Fang, 方世杰
• Other Authors: 李文達
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/5kej9u

碩士 === 國立臺北科技大學 === 電資碩士班 === 97 === With the progress of information science and technology, the request for transmission speed is more and more faster, and that assure accuracy of the correct information is very important. Among error correcting codes, RS (Reed-Soloman) codec is practical and suitable for use in modern communication system. In this thesis, a Reed-Solomon codec hardware (255,239,16) is proposed for communication system. First, we can calculate the Syndrome value. Second, we find the Error Location Polynomial and Error Evaluate Polynomial. Finally, the error is corrected by “Chien Search” and “Forney” circuit, and that the VLSI architecture of RS codec is also proposed. For the hardware implementation, Verilog Hardware Description Language is used to design and simulated by Modelsim system. For demonstrating this architecture, RS codec function is verified by Xilinx Vertex ІV XC4VSX35 FPGA platform, and use the ChipScope system to monitor results. The experimental results show that the maximum frequency of this RS codec is 111MHz, the decode frequency is 313Mbit/s, and prove this decoder can correct burst errors effectively, that is suitable for the high speed communication system.