A Wide-Range Phase-Locked Loop with Low Voltage and Noise-Immunity for USB 2.0

• Main Authors: Chi-Hsiung Wang, 王吉雄
• Other Authors: Jen-Shiun Chiang
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/22228248259124081147

碩士 === 淡江大學 === 電機工程學系碩士班 === 97 === Nearly 30 years ago, PLL (Phase-Locked Loop, PLL) has been widely used in various research fields, including signal generators, frequency synthesizers, clock and data recovery and so on. The main function of PLL is phase locked. The applications of PLL can make frequency become faster, and make the chip''s internal phase delay bias, leading to transmission of data errors. The emphasis on the era of high-speed transmission, PLL must have high noise immunity. There are some problems in circuits such as Jitter, Phase Error, as well as the Power Supply Noise. Because the requirement of the system frequency becomes faster and faster, power consumption becomes large. PLL is another topic of how to reduce power consumption, and in line with the specifications of today''s electronic systems. This paper is mainly to reduce the power consumption of PLL by using low-voltage and expand the range of frequency. In this paper, switching current is adopted so wide-range PLL with low-voltage can be performed for USB 2.0.