A Wide-Range Phase-Locked Loop with Low Voltage and Noise-Immunity for USB 2.0
碩士 === 淡江大學 === 電機工程學系碩士班 === 97 === Nearly 30 years ago, PLL (Phase-Locked Loop, PLL) has been widely used in various research fields, including signal generators, frequency synthesizers, clock and data recovery and so on. The main function of PLL is phase locked. The applications of PLL can make f...
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ndltd-TW-097TKU054420242015-10-13T16:13:31Z http://ndltd.ncl.edu.tw/handle/22228248259124081147 A Wide-Range Phase-Locked Loop with Low Voltage and Noise-Immunity for USB 2.0 適用於USB2.0的寬頻操作具有低電壓及抗雜訊之鎖相迴路 Chi-Hsiung Wang 王吉雄 碩士 淡江大學 電機工程學系碩士班 97 Nearly 30 years ago, PLL (Phase-Locked Loop, PLL) has been widely used in various research fields, including signal generators, frequency synthesizers, clock and data recovery and so on. The main function of PLL is phase locked. The applications of PLL can make frequency become faster, and make the chip''s internal phase delay bias, leading to transmission of data errors. The emphasis on the era of high-speed transmission, PLL must have high noise immunity. There are some problems in circuits such as Jitter, Phase Error, as well as the Power Supply Noise. Because the requirement of the system frequency becomes faster and faster, power consumption becomes large. PLL is another topic of how to reduce power consumption, and in line with the specifications of today''s electronic systems. This paper is mainly to reduce the power consumption of PLL by using low-voltage and expand the range of frequency. In this paper, switching current is adopted so wide-range PLL with low-voltage can be performed for USB 2.0. Jen-Shiun Chiang 江正雄 2009 學位論文 ; thesis 107 zh-TW |
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碩士 === 淡江大學 === 電機工程學系碩士班 === 97 === Nearly 30 years ago, PLL (Phase-Locked Loop, PLL) has been widely used in various research fields, including signal generators, frequency synthesizers, clock and data recovery and so on. The main function of PLL is phase locked. The applications of PLL can make frequency become faster, and make the chip''s internal phase delay bias, leading to transmission of data errors.
The emphasis on the era of high-speed transmission, PLL must have high noise immunity. There are some problems in circuits such as Jitter, Phase Error, as well as the Power Supply Noise. Because the requirement of the system frequency becomes faster and faster, power consumption becomes large. PLL is another topic of how to reduce power consumption, and in line with the specifications of today''s electronic systems.
This paper is mainly to reduce the power consumption of PLL by using low-voltage and expand the range of frequency. In this paper, switching current is adopted so wide-range PLL with low-voltage can be performed for USB 2.0.
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author2 |
Jen-Shiun Chiang |
author_facet |
Jen-Shiun Chiang Chi-Hsiung Wang 王吉雄 |
author |
Chi-Hsiung Wang 王吉雄 |
spellingShingle |
Chi-Hsiung Wang 王吉雄 A Wide-Range Phase-Locked Loop with Low Voltage and Noise-Immunity for USB 2.0 |
author_sort |
Chi-Hsiung Wang |
title |
A Wide-Range Phase-Locked Loop with Low Voltage and Noise-Immunity for USB 2.0 |
title_short |
A Wide-Range Phase-Locked Loop with Low Voltage and Noise-Immunity for USB 2.0 |
title_full |
A Wide-Range Phase-Locked Loop with Low Voltage and Noise-Immunity for USB 2.0 |
title_fullStr |
A Wide-Range Phase-Locked Loop with Low Voltage and Noise-Immunity for USB 2.0 |
title_full_unstemmed |
A Wide-Range Phase-Locked Loop with Low Voltage and Noise-Immunity for USB 2.0 |
title_sort |
wide-range phase-locked loop with low voltage and noise-immunity for usb 2.0 |
publishDate |
2009 |
url |
http://ndltd.ncl.edu.tw/handle/22228248259124081147 |
work_keys_str_mv |
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