| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 97 === A phase-locked loop (PLL) is a widely used circuit in modern radio communication systems. Traditionally, a PLL is made as an analog building block. However, integrating an analog PLL in a digital noisy systems-on-a -chip (SoC) environment is challenging. In addition, the analog PLL is sensitive to process parameters. It is too hard to use the same analog PLL design in different process. On the other hand, The ADPLL has no off-chip components. it is made from standard cells found in most digital standard cell libraries. Therefore, The ADPLL has the higher immunity for supply noise, and temperature variation, and process.
In this thesis, The ADPLL consists of a digital phase frequency detector, a digital loop filter, a digital controlled ring oscillator and frequency divider. This thesis proposed a new architecture of Time-to-Digital converter to get digital phase error. The simulation results show that when reference clock is 20 MHz. The locking time is 6.674us (simulation). Working frequency ranges for this ADPLL is about 152~581MHz. The ADPLL are developed by VHDL (VHSIC Hardware Description Language), and they are simulated with Xilinx Spartan3E XC3S1600E-5FG320 FPGA by ModelSim 6.1i and Xilinx ISE 8.2i to justify the feasibility of the proposed ADPLL .
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