DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS
碩士 === 大同大學 === 電機工程學系(所) === 97 === A phase-locked loop (PLL) is a widely used circuit in modern radio communication systems. Traditionally, a PLL is made as an analog building block. However, integrating an analog PLL in a digital noisy systems-on-a -chip (SoC) environment is challenging. In addit...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/48811008021719126435 |