IMPLEMENTATION OF HIGH SPEED ARCHITECTURE FOR AES-OCB ALGORITHM
碩士 === 大同大學 === 電機工程學系(所) === 97 === ABSTRACT The Advanced Encryption Standard (AES) algorithm has become the default choice for many security services in numerous applications. In this thesis, we propose a high speed, 10-pipelined FPGA implementation of the AES-OCB (Offset Codebook) cipher usi...
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/44228649701247392896 |
| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 97 === ABSTRACT
The Advanced Encryption Standard (AES) algorithm has become the default choice for many security services in numerous applications. In this thesis, we propose a high speed, 10-pipelined FPGA implementation of the AES-OCB (Offset Codebook) cipher using Xilinx development tools and Virtex-4 XC4VLX60-10ff1148 FPGA circuits. IEEE 802.11 defines the AES-based cipher system, one of them is operated on OCB mode. All the modules in this chip are described by using Verilog language. The developed AES-OCB chip is aimed at providing high speed with sufficient security. The operation data path operates at 98MHz resulting in a throughput of 1573 Mbits/sec. A comparison is provided between our design and similar existing implementations.
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