| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 97 === The circuit design is oriented to the goal of shrinking area、low power dissipation and high data transmission. Let all system components can be integrated on a chip. Hence our thesis aim at shrinking the area of LC tank 、promoting the Q factor of inductor and increasing negative-resistance, so as to arrive at the target of shrinking area and low power dissipation. In our thesis, we talk about the theory and architecture of oscillator, and we will use the LC oscillator which is the most popular for analysis. The chip fabrication of VCO circuit is made by TSMC 0.18um CMOS 1P6M process. Finally, the efficiency of the circuit was demonstrated by measurement.
The first chip was designed a low power and wide tuning range CMOS LC voltage controlled oscillator (VCO) with back-source transformer feedback. The measurement result of the VCO exhibits a tuning range of 22% form 4.41GHz to 5.49GHz at the supply voltage of 0.8 V. The figure of merit, core power consumption and output power are -186.36 dBc/Hz, 2.4mW and -4.65 dBm, respectively. The phase noise is -116.36 dBc/Hz at the operation frequency of 4.9 GHz.
The second chip was designed a low phase noise and wide tuning range CMOS LC voltage controlled oscillator (VCO) with gate-drain transformer feedback. The measurement result of the VCO exhibits a tuning range of 28% form 4.39GHz to 5.8GHz at the supply voltage of 0.8 V. The figure of merit, core power consumption and output power are -193.1 dBc/Hz, 4.4mW and -2.3dBm, respectively. The phase noise is -124.3dBc/Hz at the operation frequency of 5.8 GHz.
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