A Spread Spectrum Clock Generator Using Capacitive Multiplication and Digital Modulation Techniques

• Main Authors: Jia-Hau Li, 李家豪
• Other Authors: Chorng-Sii Hwang
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/46593412359947486346

碩士 === 雲林科技大學 === 電機工程系碩士班 === 97 === In today’s computer systems, high speeds are demands. When operating at high frequencies, the problem of Electro-Magnetic Interference (EMI) will be increase and it will affect the accuracy of the system. A lot of methods have been proposed to diminish EMI, but all the methods have advantages and disadvantages. Among these solutions, spread spectrum is the easiest and the most efficient one. Because of the process and the design idea is improved, System-on-Chip (SoC) is the master stream for integrated-circuit. The transistor size is getting smaller and smaller but the passive component is not easy to implement on-chip. Low-Pass-Filter is one of the modules in the PLL. Low-Pass-Filter includes resistor and capacitor. At the present day, in order to save the chip area and cost, most of the Low-Pass-Filter are off-chip, but let all of the system fully on-chip is the concept of the SoC. If we want to diminish the chip area, we have to let the capacitor as smaller as possible. The capacitive multiplication techniques will be used to achieve this goal. In chapter 2, we will give the basic ideas of PLL and derive proper design flows. Also a rough design flow is described along with detailed parameter setting. In chapter 3, we introduced spread spectrum clock generator and the basic ideas of capacitive multiplications techniques at first. After that, we describe that all of the capacitive multiplications techniques have been proposed. We also use the circuit module to improve the capacitive multiplications techniques were made the same effect with the traditional architecture. In Chapter 4, A spread spectrum clock generator using capacitive multiplication and digital modulation techniques will be proposed and the loop filter will be designed on-chip by capacitive multiplication technique. In chapter 5, it is the conclusion of the thesis. We use TSMC CMOS 0.18μm 1P6M to fabricate and take advantage of the simulation tools to improve my architecture. Key Word: phase-locked loop，spread spectrum clock generator，capacitive multiplication techniques