Design of Base-band Circuits for OFDM System and Beamformer Based on SDR Structure

博士 === 元智大學 === 通訊工程學系 === 97 === Based on software defined radio (SDR) structure, the baseband circuits of the orthogonal frequency division multiplexing (OFDM) system and smart an-tenna are designed in the dissertation. It includes four major research items. In chapter 2, for the purpose of reduci...

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Bibliographic Details
Main Authors: You-Rong Lin, 林侑融
Other Authors: Jeich Mar
Format: Others
Language:en_US
Published: 2009
Online Access:http://ndltd.ncl.edu.tw/handle/55014881095476265711
Description
Summary:博士 === 元智大學 === 通訊工程學系 === 97 === Based on software defined radio (SDR) structure, the baseband circuits of the orthogonal frequency division multiplexing (OFDM) system and smart an-tenna are designed in the dissertation. It includes four major research items. In chapter 2, for the purpose of reducing the quantization noise and power con-sumption of UWB-OFDM transceiver, a new time domain-based interpolator and decimator structure is proposed to realize five-bit 128-tone sigma-delta modulation (SDM) D/A and A/D converters. In chapter 3, a SDR channel simulator is designed for testing the base band transceiver of various wireless communication systems. The proposed SDR architecture and the hardware re-configuration scheme are used to reconfigure the processing modules when the channel conditions are changed. In chapter 4, the hardware reconfiguration feature of a SDR architecture can support multiple modes of digital beam-former (DBF) striving for compactness and efficient processing power, which are the important issues for the micro-satellite SAR systems. In chapter 5, based on the SDR structure, an active phased array radar system consisting of the 16-QAM and 64-QAM multi-carrier direct sequence spread spectrum (MC-DSSS) waveforms for target range and velocity measurement is pro-posed. In addition, the radar baseband receiver and the FFT-based multi-mode DBF are realized in the field programmable gate array (FPGA) for the target DOA measurement and jamming cancellation to demonstrate the function of the hardware reconfiguration.