Low Complexity H.264/AVS Dual-Mode Predictive Pixel Compensator for HDTV Applications
碩士 === 國立中正大學 === 資訊工程所 === 98 === In this thesis, we propose a low-complexity H.264/AVS dual-mode predictive pixel compensator (PPC) for the motion compensation. PPC increases 37% hardware cost to support H.264 and AVS standards. With comparison of other works, there is lower computational complexi...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/32824047627504867239 |
| Summary: | 碩士 === 國立中正大學 === 資訊工程所 === 98 === In this thesis, we propose a low-complexity H.264/AVS dual-mode predictive pixel compensator (PPC) for the motion compensation. PPC increases 37% hardware cost to support H.264 and AVS standards. With comparison of other works, there is lower computational complexity in PPC. In intra prediction, we design a shared adder-based architecture for both H.264 and AVS intra modes. It reduces computational complexity in both H.264 I4MB prediction mode 3-8 computation and AVS I8MB prediction modes up to 50%. Furthermore, we improve the hardware utilization by using the distributed memory access that reduces memory buffer sizes for storing neighboring pixels. In inter prediction, we can save about 48% of external memory bandwidth by data reuse through hybrid block size memory access. We design a mixed six-tap FIR filter for H.264/AVS luma interpolation which effectively reduces hardware cost up to 55%. The hardware cost of the proposed design is about 61.9K gates and 8.3K bits of local memory by using UMC 90nm CMOS technology to operate at 339 MHz in maximum. It achieves the real-time processing requirement for motion compensation on maximum resolution of 4096x2304@30fps video for 16:9 applications.
|
|---|