Performance study of applying RSCE and ABB techniques in nano-CMOS circuits
碩士 === 國立中正大學 === 電機工程所 === 98 === There are more special process procedures in nano era which changed the characteristic of semiconductor. The performance and energy consumption will get lost once designer still keep the same design technique without process consideration. A special byproduct calle...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/74518827501245327165 |
| Summary: | 碩士 === 國立中正大學 === 電機工程所 === 98 === There are more special process procedures in nano era which changed the characteristic of semiconductor. The performance and energy consumption will get lost once designer still keep the same design technique without process consideration. A special byproduct called reverse short channel effect (RSCE) which can improve the circuit performance is involved. This paper will explore the circuit performance by utilizing UMC 55 nm process with adaptive body bias technique.
At present, foundry didn’t provide the special model for sub-threshold circuit design application. It is difficult to design a sub-threshold circuit due to the uncertainly of circuit and process variation. This paper first will focus on the impact of threshold voltage at sub-threshold operation, then explore the design consideration at sub-threshold operation. This paper presents a novel methodology to combine reverse short-channel effect (RSCE) application and adaptive body bias. This paper is also describes a device size optimization which be considered for both sub-threshold and super-threshold operation. Experiment results using 64 bits Carry look-ahead adder and fabricated in UMC 55 nm CMOS technology show that the critical path delay, power consumption.
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