| Summary: | 碩士 === 長庚大學 === 電子工程學系 === 98 === This thesis presents the development of RF CMOS circuits for 24GHz transceivers including high gain, low power, low noise amplifier and low power down-conversion mixer with TSMC 90nm RF CMOS standard process and 0.13µm RF CMOS standard process. All circuits were simulated and designed by Agilent ADS (Advanced Design System) software. The CMOS RF receiver is focused on low power consumption, and operated at frequency of 24GHz. This work includes low-noise amplifier and down-conversion mixer. The operating radio frequency is 24GHz, and the supply voltage is 1.2V.
In this thesis, the low-noise amplifier has a power gain of 18.212dB and noise figure of about 2.977dB. Input and output return losses are smaller than -15dB and power consumption of 2.87mW and chip area of 0.796x0.703mm2. Low power down conversion mixer shows a conversion gain of 7.237dB and the return loss of RF Port is smaller than -12dB. Power consumption is 8.07mW, and IIP3 of -3.7dBm. The LO to BB isolation and RF to BB isolation are -30dB and -30dB, respectively. The chip area is 0.89407x0.58mm2.
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