Development of the Robustness Verification and Analysis Tool for SoC Design Platform

• Main Authors: Chen Sin-Yu, 陳信宇
• Other Authors: Chen Yung-Yuan
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/63260286163957388938

碩士 === 中華大學 === 資訊工程學系(所) === 98 === Intelligent embedded systems are getting prevalent in highly reliable applications, such as intelligent vehicle systems and intelligent robots. Nowadays, the intelligent systems employ the concept of system on chip (SoC) design, and by the coming of very deep submicron process, the interference of electromagnetic and radiation are prone to occur in the high density system chip, and therefore, decrease the SoC reliability. Thus, the designers should deal with the SoC reliability problem seriously when designing new intelligent systems. In this paper, we develop a robustness verification and analysis tool for SoC design platform. The proposed tool uses the software-implemented fault injection methodology to inject the faults into the registers of a CPU. An approach to classify the failure modes of SoC is proposed, and implemented in the proposed tool to assist us in understanding the system failure behaviors, verifying the SoC robustness and identifying the weakness points. Then we can improve the weakness points by adding fault tolerance to the SoC to enhance its reliability. Our tool provides automatic fault injection, failure mode classification and calculation of probability distribution of failure modes. As a result, our tool can raise the efficiency of SoC design and verification. An ARM-based system platform was used to demonstrate our tool. We can classify seven different failure modes when faults were injected into the registers of ARM CPU and the probability distribution of these failure modes was computed. Based on the probability distribution of failure modes, the robustness of the system can be identified.