Performance Optimization for Multi-Core Cache Coherent Systems Using NoC-Assistant Mechanisms
碩士 === 逢甲大學 === 資訊工程所 === 98 === The significant speed-gap between processor and memory makes last-level cache performance crucial for Chip Multiprocessors (CMPs). Non-uniform cache architecture (NUCA) has been proposed to overcome performance limit in CMPs in many embedded applications. This design...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/19916755923660118361 |