A 6-bit 1GSPS Flash ADC with Step-Shifted Background Calibration
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === In this thesis, a 6-bit 1GSPS Flash ADC is implemented, and a background offset calibration circuit is proposed to calibrate the offset of the preamplifier and the latch due to mismatch. By using the switches for resistor ladder, the 1LSB step-shifted voltage...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/96974104278031857942 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === In this thesis, a 6-bit 1GSPS Flash ADC is implemented, and a background offset calibration circuit is proposed to calibrate the offset of the preamplifier and the latch due to mismatch. By using the switches for resistor ladder, the 1LSB step-shifted voltage from its reference voltage is generated. The probability of the input signal hitting into the same thermometer code would be not be the same in differential step-shifted. According to the output thermometer code and use the DAC with the ripple counter circuit to calibrate the offset. The two-level step-shifted method is proposed for higher resolution.
A 6-bit 1G Sample/s flash ADC is implemented by TSMC 0.13um 1P8M CMOS process. Simulation results show that SNDR is 37dB with 441MHz input frequency at 1GHz sample rate. The power consumption is 13.2mW with a 1.2-V supply where output buffers are excluded.
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