A 6-bit 1GSPS Flash ADC with Step-Shifted Background Calibration
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === In this thesis, a 6-bit 1GSPS Flash ADC is implemented, and a background offset calibration circuit is proposed to calibrate the offset of the preamplifier and the latch due to mismatch. By using the switches for resistor ladder, the 1LSB step-shifted voltage...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/96974104278031857942 |