| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === A comparator-based switched-capacitor (CBSC) circuit topology is introduced comprehensively, it replaces the operational amplifier by a threshold-detection comparator and current sources, then the power consumption and active area can be decreased. However, the overshoot voltage affects the resolution and the two charge transfer phases limit the sampling frequency. This thesis propose a new method of charge transferring to solve the overshoot problem and increase the sampling speed. To obtain the precise output value, the proposed architecture adjusts the reference voltage of comparator by sampling the overshoot voltage. Moreover, there is only one current source of this structure, the sampling frequency is increased.
This second-order ΣΔ ADC with a 1.8-V supply voltage has been designed in 0.18-μm CMOS process without low threshold MOS devices. The modulator achieves 52-dB SNDR within the signal bandwidth of 781.25 kHz, the sampling frequency is 50 MHz, which corresponds to an oversampling ratio of 32, the total power consumption is 3.85 mW.
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