| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === H.264/AVC, the video compression standard, plays an important role of the multimedia in recent years, because H.264 can achieve better coding efficiency than previous video coding standards with the same video quality.
To have such excellent compression efficiency, H.264 pays cost. The encode features can significantly reduce coding redundancy, but increase computational complexity by using motion compensation (including multiple reference frames, variable block size motion estimation and quarter-sample-accuracy motion vector), intra prediction and context-based adaptive entropy coding, such as CAVLC or CABAC.
Within H.264 intra prediction, there are nine 4×4 luminance prediction modes, four 16×16 luminance prediction modes, and four 8×8 chrominance prediction modes. And the mode decision chooses the best mode by using rate-distortion optimization (RDO). If the encode obtains both good quality and high efficiency, it requires large amounts of RDO calculations.
This thesis presents a mode selection approach to reduce computational time by using fast direction detection algorithm. We verify the proposed algorithm through the reference software Joint Model and implement the RTL code by Verilog hardware description language. We synthesize the digital circuit by using Design Compiler of Synopsys with the TSMC 0.18μm CMOS technology. Finally, the proposed intra prediction algorithm can reduce 70% computational time and the low complexity hardware can work up to 202MHz.
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