| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 98 === In this thesis, two circuits are proposed. The first one is a 10-bit source driver for the TFT-LCD panel, and the second one is a 2GHz samples/s 6-bit Flash ADC.
In the first circuit, the two-stage resistive divider DAC is adopted for the 10-bit source driver. The 10-bit decoder is divided into 6-bit and 4-bit to effectively reduce chip area. The new technique, a current-injection DAC, is proposed to overcome the loading problems of the two-stage architecture. Besides, a new output buffer for the source driver is introduced to save more power. The simulation result of the INL range is 0.07LSB~-0.3LSB, and the DNL range is 0.3LSB~-0.03LSB. The chip area is 0.0215mm2 per channel.
In the second part of this thesis, A 6-bit Flash ADC with 2GHz samples/s is presented. The design considerations and analyses for the block circuits of ADC, like the track and hold circuit, the preamplifier, and the comparator are also explained in detail. To alleviate the random offset caused by the process variation, the resistive averaging technique is adopted. The simulation result for the ENOB of this ADC is 5.8-bit when the input frequency is 996MHz. The chip area is 1.9mm2.
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