Design and Implementation of 24GHz RF Receiver Front-End Circuits

• Main Authors: Chiu-Hsuan Wang, 王秋瑄
• Other Authors: Yo-Sheng Lin
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/43150598518808785613

碩士 === 國立暨南國際大學 === 電機工程學系 === 98 === The thesis mainly uses CMOS process technology to implement the RF receiver front-end circuit, operating frequency at 24GHz and UWB system ,Study the theme can be divided into three parts： In the first part, application at UWB low noise amplifier, use the TSMC 0.18um one-poly-six-metal (1P6M) CMOS process. This study use two stage inverter with splitting-load inductive peaking techniques realize the low noise amplifier, and use two inductance at second stage inverter ,which to achieve wideband、low noise、figure、low power consumption and have good impedance matching. In the second part, the low-noise amplifier which is implemented by the TSMC 0.13um CMOS process can be used for a 24-GHz short-range automotive collision avoidance radar system. In order to obtain a high power gain, we used four stage and conjugate matching techniques between each stage. The first stage is common source amplifier. Simple topology at first stage can achieve low noise figure. The second stage uses the Resistance-feedback to limit the supply voltage for low power consumption. The Current-reuse technique is adopted in the third and the fourth stage to reduce power dissipation. The experimental results showed that High 15dB gain, S11 below -14.4 dB, the least noise figure of 3.16dB at 24GHz, and the flat noise figure only 3.2~ 3.7 dB for 21-27GHz, consuming power of 22.07 mW, chip area of 0.67 mm2, group-delay-variation of ±17.82 ps, and have figure of merit (FOM) of 2.57, The results show that the LNA is suitable for high resolution radar systems. The third part is applied to the receiver of front-end. The circuit includes LNA and Mixer. The low noise amplifier both use current reuse techniques to reduce low power. In this section we introduce two type mixers ,single-balance mixer and dual-gate mixer. The dual-gate Mixer is utilized on the stable current method in the first stage and cascode method in the second stage, which can achieve lower current consumption and larger gain, the measurement performance is 21.32dB of power gain at 24GHz. The 3-port isolation performance is better than 29.5dB, and the input third-order intercept point is -11dBm while the consuming power is 45mW. For two type , we implemented in TSMC 0.18um one-poly-six-metal (1P6M) CMOS process.