| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 98 === The storage component of SSD is NAND flash memory, it has shock resistance and high speed of read operation. SSD uses multi-channel architecture for increasing speed of read/write operation. Therefore the storage size of SSD and flash chips in it is increasing such that a request does not cause all chips to work, and some chips are idle. A device can service up to one request at a time, and OS separates the sequential read access to many requests to command the device. We proposed a prefetch policy for predicting sequential read access, and hoped to connect the sequential read requests. By this way it could speed up the progress of sequential read access on SSD. Then we also observe the effect of prefetch on different hardware architectures. Finally, our prefetch policy used on the SSD architecture with 8-channel and four flash chips in each channel can improve about 22.5%.
|
|---|
