| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 98 === An increasing interest has been drawn in the design for manufacturing (DFM) problems. One of the heavily surveyed DFM problems is the formulation and reduction of critical area for random defects. The effect of random defects, which do not shrink with the manufacturing process, has become one of the key yield-related factors in advanced processes. In order to improve the sensitivity to random defects, arranging interconnects has been proven to be an effective approach. Among the design flow, track routing is an ideal stage for DFM issues because it quickly arranges physical interconnects to proper locations. Other than track routing, layer assignment has also found to be a promising step for DFM issues.
This paper proposes an integration of gridless track routing and layer assignment with random defect awareness, RAAT. Two problems has been defined in this work, which are the obstacle-aware layer assignment and the POF (probability of failure)-friendly wire ordering. Utilizing conventional approaches used for placement and floorplanning like min-cut partitioning, RAAT could arrange and assign interconnects efficiently. Experimental results show the necessity of the integration of layer assignment and track routing. Meanwhile, RAAT could not only finish each case quickly but also achieves higher completion rate. In addition, RAAT also reduces 10% of the number of failure at most in Monte Carlo simulation compared to previous works.
|
|---|
