Ultra-Low Voltage PVT-Robust Clock System Design for Sub/Near-Threshold Green Technologies
碩士 === 國立交通大學 === 電子研究所 === 98 === This thesis proposes an ultra-low voltage (ULV) PVT-robust clock system for sub/near-threshold green technologies. For variation-aware circuit design, the unified logical effort models are proposed, which have been established over the four different nanoscale CMOS...
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/70403455327929619389 |